1. Field
The present disclosure relates generally to integrated circuits, and more particularly, to a timing circuit for memory.
2. Background
A read word line is asserted during a read operation of memory cells. When the read word line is asserted, memory cells connected to that read word line provide their stored value/bit to a read bit line that is connected to a sense amplifier. If enabled at the appropriate time (e.g., when the read bit line is provided with the stored value/bit), the sense amplifier can detect the value/bit in the read bit line. A memory timing circuit may be used to determine the appropriate time to enable the sense amplifier. The memory timing circuit may generate a timing signal that closely tracks/emulates the signal in the read word line. However, variations in process, voltage, and/or temperature (PVT) conditions can affect the timing signal such that the timing signal does not closely track/emulate the signal in the read word line. Accordingly, there is a need in the art for a timing circuit that is resilient to variations in PVT conditions such that the timing signal closely tracks/emulates the signal in the read word line despite variations in PVT conditions.